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| 書本編號 |
：ISBN 0471429767 |
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| 書名 |
| ： | Verilog Coding for Logic Synthesis |
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| 書本訂價 |
：980元 |
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| 書本賣價 |
：490元
(需另加運費:$20)
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| 推薦給朋友 |
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| 書本描述 |
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Provides a practical approach to Verilog design and problem solving.
* Bulk of the book deals with practical design problems that design engineers solve on a daily basis.
* Includes over 90 design examples.
* There are 3 full scale design examples that include specification, architectural definition, micro-architectural definition, RTL coding, testbench coding and verification.
* Book is suitable for use as a textbook in EE departments that have VLSI courses
Table of Contents
Table of Figures.
Table of Examples.
List of Tables.
Preface.
Acknowledgments.
Trademarks.
Introduction.
Asic Design Flow.
Verilog Coding.
Coding Style: Best-Known Method for Synthesis.
Design Example of Programmable Timer.
Design Example of Programmable Logic Block for Peripheral Interface.
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| 推薦此書本 |
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| 目前有 0 人推薦 |  |
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